1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to the lithographic production of semiconductor devices on a wafer.
2. Description of Related Art
Integrated circuit devices are fabricated principally by lithographic methods in spaced chiplets arranged on the semiconductor wafer surface. Front-end-of-the-line (FEOL) denotes the first portion of integrated circuit fabrication where the individual active circuit devices are patterned in chiplet regions on the wafer surface, while back-end-of-line (BEOL) denotes the portion of fabrication where the metal wiring layers for the devices are deposited. The chiplets are separated by regions on no, non-active, and/or electrical test features known as kerf regions, which provide space for the chiplets to be cut apart or diced to produce individual integrated circuit chips. Variation in pattern density within chiplets, from chiplet to chiplet, and chiplet to kerf results in severe topography differences in the BEOL. Undesirable BEOL topographical variations may result after attempts at planarizing by chemical-mechanical polishing (CMP), where regions relatively devoid of areas of metal (e.g., vias or lines) polish at rates significantly lower than those areas having a high density of metal. The BEOL topography results in a very limited common process window across the entire field, and some features printing at very different sizes due to focus offsets within the field. Solutions that have been implemented previously include rearranged the field layout so that the chiplet-kerf pattern density data (change) does not greatly tilt the focal plane. Other solutions have been proposed, such as those in U.S. Pat. No. 6,593,226, in which CMP process benchmarking is required and an algorithm is determined for iterative dummy feature placement optimization.